Design and analysis of tunable analog circuit using double gate MOSFET at 45nm CMOS technology

R. Kushwah, S. Akashe
{"title":"Design and analysis of tunable analog circuit using double gate MOSFET at 45nm CMOS technology","authors":"R. Kushwah, S. Akashe","doi":"10.1109/IADCC.2013.6514465","DOIUrl":null,"url":null,"abstract":"In this paper, we included designing of low power tunable analog circuits using double gate (DG) MOSFET, where the front gate output is changed by control voltage on the back gate. The DG devices can be used to improve the performance and reduce the power dissipation when front gate and back gate both are independently controlled. In this paper, we included the analysis of the analog tunable circuits such as CMOS Amplifier pair, Schmitt Trigger circuit and Operational trans-conductance Amplifier. Gain, phase and output response of analog tunable circuits have been illustrated in the paper. These circuit blocks are used for low-noise high-performance integrated circuits for analog and mixed-signal applications. The simulation results are predicted by Cadence Virtuoso Tool in 45nm complementary metal oxide semiconductor (CMOS) Technology.","PeriodicalId":325901,"journal":{"name":"2013 3rd IEEE International Advance Computing Conference (IACC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 3rd IEEE International Advance Computing Conference (IACC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IADCC.2013.6514465","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

In this paper, we included designing of low power tunable analog circuits using double gate (DG) MOSFET, where the front gate output is changed by control voltage on the back gate. The DG devices can be used to improve the performance and reduce the power dissipation when front gate and back gate both are independently controlled. In this paper, we included the analysis of the analog tunable circuits such as CMOS Amplifier pair, Schmitt Trigger circuit and Operational trans-conductance Amplifier. Gain, phase and output response of analog tunable circuits have been illustrated in the paper. These circuit blocks are used for low-noise high-performance integrated circuits for analog and mixed-signal applications. The simulation results are predicted by Cadence Virtuoso Tool in 45nm complementary metal oxide semiconductor (CMOS) Technology.
45纳米CMOS双栅MOSFET可调谐模拟电路的设计与分析
在本文中,我们使用双栅MOSFET设计了低功率可调模拟电路,其中前门输出由后门上的控制电压改变。当正门和后门都独立控制时,DG器件可以提高性能,降低功耗。本文对CMOS放大器对、施密特触发电路和运算跨导放大器等模拟可调谐电路进行了分析。文中给出了模拟可调谐电路的增益、相位和输出响应。这些电路模块用于模拟和混合信号应用的低噪声高性能集成电路。利用Cadence Virtuoso工具对45纳米互补金属氧化物半导体(CMOS)技术的仿真结果进行了预测。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信