Cantilever NEMS relay-based SRAM devices for enhanced reliability

Abstract

We analyze the benefits of replacing selected MOSFET transistors by nanoelectromechanical relays within conventional CMOS six transistor SRAM cells. Specifically, we evaluate a potential implementation that uses a cantilever designed with a 65 nm standard CMOS technology. The impact on various reliability metrics like static noise margin and write noise margin are evaluated from circuit simulations using a nanomechanical relay Verilog-A compact model. Comparisons are performed between a 65 nm CMOS 6T conventional SRAM cell and various hybrid memory cells constructed by replacing selected MOSFET transistors with cantilever relays. The impact on other important memory cell parameters such as area, timing performance and power consumption is also discussed.