{"title":"VHDL modelling and simulation of parallel-beam filtered backprojection for CT image reconstruction","authors":"Pranamita Basu, M. Manjunatha","doi":"10.1109/MSPCT.2009.5164213","DOIUrl":null,"url":null,"abstract":"This paper describes the VHDL modelling and simulation of parallel-beam filtered backprojection algorithm to be used for image reconstruction in CT (computed tomography). The algorithm being highly data intensive and computationally extensive requires a lot of time for execution and hence it necessitates hardware implementation for real-time processing. So the VHDL model can be implemented on reconfigurable hardware. Due to memory constraints a smaller size image has been implemented on FPGA while the VHDL model has been designed for a 512×512 image which can be implemented on FPGA using offchip memory blocks.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Multimedia, Signal Processing and Communication Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MSPCT.2009.5164213","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper describes the VHDL modelling and simulation of parallel-beam filtered backprojection algorithm to be used for image reconstruction in CT (computed tomography). The algorithm being highly data intensive and computationally extensive requires a lot of time for execution and hence it necessitates hardware implementation for real-time processing. So the VHDL model can be implemented on reconfigurable hardware. Due to memory constraints a smaller size image has been implemented on FPGA while the VHDL model has been designed for a 512×512 image which can be implemented on FPGA using offchip memory blocks.