Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint

Abstract

We have comprehensively studied feasibility of single-fin (1-fin) devices from viewpoint of scaling switching energy (CV²) and device footprint width, which affects standard cell height. We have clarified methodology to lower minimum operation voltage (Vmin) of flip-flop (F/F) featuring 1-fin devices in order to maximize gain of CV². For the first time, we have demonstrated Vmin of 1-fin F/F same as 2-fin one and 27% CV² reduction with keeping speed at a constant leakage.