An Embedded Load Balancing System for High Speed OC192 Networks

Abstract

Parallel architecture has been used for packet processing of high speed links. Essential to such architecture is a load balancer which responsible for packet dispatching. In this paper, we design an embedded system for high speed OC192 network traffic load balancing. In the system, incoming traffic is load-balanced to 12 processing engines through Ethernet. In order to reasonably dispatch traffic while preserving the order of packets within a flow, we propose a novel feedback-based load balancing algorithm. For each packet, we calculate the hash value on source and destination IP addresses. The return value is used as an index to a lookup table to retrieve a target processing engine. The lookup table is adjusted according to feedback. Effectiveness of the algorithm is evaluated by simulations using real network trace. We implement the system in Field Programmable Gate Array (FPGA) and verify it by experiments. Experimental results show that the system sustains 10Gbps throughputs with an average delay of 4.2 microseconds. The system has been used in a practical network monitoring application.