Study of layout extraction accuracy on W/L estimation of ELT in analog design flow

G. Cardoso, T. Balen
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引用次数: 6

Abstract

This paper presents an investigation regarding the model adopted by a commercial layout extraction tool to estimate the aspect ratio (W/L) of enclosed layout transistors (ELT). The method used by the EDA (Electronic Design Automation) tool to obtain an equivalent W/L is compared with well know mathematical models presented on the literature. The influences in the aspect ratio estimation regarding designer-controlled layout variables are also target of investigation. Results indicate that the EDA tool analyzed in this work, overestimates the extraction of aspect ratio from ELT layout, when compared with a more accurate mathematical model used to calculate the effective aspect ratio of square ELT devices. The results also show that designer-controlled layout variables may contribute to increase the divergences among the extraction tool method and the studied models in the estimation of the ELT aspect ratio.
模拟设计流程中ELT的W/L估计的版图提取精度研究
本文研究了一种商用版图提取工具用于估算封闭版图晶体管宽高比(W/L)的模型。将EDA(电子设计自动化)工具用于获得等效W/L的方法与文献中给出的已知数学模型进行了比较。设计师控制的布局变量对纵横比估计的影响也是研究的目标。结果表明,与用于计算方形ELT器件有效长宽比的更精确的数学模型相比,本文分析的EDA工具高估了从ELT布局中提取长宽比的能力。结果还表明,设计者控制的布局变量可能会增加提取工具方法与所研究模型在ELT长径比估计中的分歧。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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