S. Pulipati, V. Ariyarathna, Udara De Silva, Najath Akram, E. Alwan, A. Madanayake, S. Mandal, T. Rappaport
{"title":"A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC","authors":"S. Pulipati, V. Ariyarathna, Udara De Silva, Najath Akram, E. Alwan, A. Madanayake, S. Mandal, T. Rappaport","doi":"10.1109/COMCAS44984.2019.8958039","DOIUrl":null,"url":null,"abstract":"This paper discusses early results associated with a fully-digital direct-conversion array receiver at 28 GHz. The proposed receiver makes use of commercial off-the-shelf (COTS) electronics, including the receiver chain. The design consists of a custom 28 GHz patch antenna sub-array providing gain in the elevation plane, with azimuthal plane beamforming provided by real-time digital signal processing (DSP) algorithms running on a Xilinx Radio Frequency System on Chip (RF SoC). The proposed array receiver employs element-wise fully-digital array processing that supports ADC sample rates up to 2 GS/second and up to 1 GHz of operating bandwidth per antenna. The RF mixed-signal data conversion circuits and DSP algorithms operate on a single-chip RFSoC solution installed on the Xilinx ZCU1275 prototyping platform.","PeriodicalId":276613,"journal":{"name":"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMCAS44984.2019.8958039","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
This paper discusses early results associated with a fully-digital direct-conversion array receiver at 28 GHz. The proposed receiver makes use of commercial off-the-shelf (COTS) electronics, including the receiver chain. The design consists of a custom 28 GHz patch antenna sub-array providing gain in the elevation plane, with azimuthal plane beamforming provided by real-time digital signal processing (DSP) algorithms running on a Xilinx Radio Frequency System on Chip (RF SoC). The proposed array receiver employs element-wise fully-digital array processing that supports ADC sample rates up to 2 GS/second and up to 1 GHz of operating bandwidth per antenna. The RF mixed-signal data conversion circuits and DSP algorithms operate on a single-chip RFSoC solution installed on the Xilinx ZCU1275 prototyping platform.