A new control structure for the pipelined CNN processor arrays

Abstract

In this paper an improvement over the control structure of the processor architecture reported in is proposed. Each processor in the array was controlled by the central control unit which proved to have some setbacks. These are: 1) the complexity of the control logic which tends to be more complicated as the number of processors gets higher; 2) the necessity to redesign the control logic for any change of the processor count in the array; 3) the problems in testability and reliability of each complex new design. Here we introduce an asynchronous control structure that eliminates problems relating to complexity, reusability and reliability.