Design and implementation of a low-phase-noise integrated CMOS Frequency Synthesizer for high-sensitivity narrow-band FM transceivers

Abstract

Frequency Synthesizers (FS) are used in a wide range of RF applications. The narrow-band FM transceivers are usually used in mobile communication network e.g. (AMPS) and public safety applications, which employ a huge number of channels in a limited bandwidth. In such applications, it is required to have a stable local oscillator (LO) signal with minimum phase noise, in order to avoid the channel interference. In this paper we present a design of a low-power low-noise integrated FS, which can be used for such applications. The circuit is capable of digitally selecting one out of 400 channels, which are closely spaced by narrow windows (25 kHz). The FS circuit is based on the charge pump phase-locked-loop (PLL) architecture. In order to cope with switching phase noise problems, we employ a programmable dual modulus divider (DMD) with a differential input prescaler and a low phase-noise LC tunable voltage controlled oscillator (VCO). We also make use of a dead-zone free phase frequency detector (PFD) with output charge pump (CP) and a third order passive loop filter. The FS is fully integrated using 0.8-micron CMOS technology on a single chip operating at 3.3 V. Being designed for narrow-band FM transceivers (operating at about 100 MHz), the single coil used in the VCO and the loop filter are placed off chip, for high-Q considerations. The integrated FS occupies 1 mm/sup 2/ areas and consumes only 6 mW. The phase noise is about -95 dBc/Hz at 25 kHz, and -122 dBc/Hz at 100 kHz.