Design of a fully digital adaptive equalizer for a 256 QAM modem

Abstract

A theoretical study of the performance and development of an equalizer that complies with the stringent specifications imposed by a 256 QAM, 2*40 Mb/s system (rate=35 Msymbol/s) is presented. Design rules for the accuracy of the internal arithmetic and A/D converters are suggested. The analysis is based on the following main parameters: (1) dynamic ranges, (2) step size and accumulator length, (3) effect of digital quantizing, and (4) arithmetic design of the correlators. An accurate theory of operation is presented with examples of simulation results.<>