Methodology for Solderability Measurement of Plated Through Holes Using Wetting Balance Test

Abstract

The goal of this work was to design a new methodology for the solderability measurement of solder alloys in vias (plated through holes) on printed circuit boards (PCB). As a key measurement device, a wetting balance tester was chosen. The sample holder was modified to be able to fix a copper tube, which simulated the plated through hole (PTH). The copper tubes were covered by a non-wetting coating on the outside; therefore, only the inside of the tube was wetted during immersion. This methodology was used for experiments with SAC305 solder in combination with colophony-based flux in order to verify its suitability. Three solder bath temperatures (255 °C, 270 °C, and 285 °C) were chosen for the measurement. The performed experiment showed the effect of a solder bath temperature and a diameter of PTH on the evaluated parameters, such as zero-cross time, non-wetting time, maximum wetting force, and height of capillary rise of the solder. The higher the temperature, the shorter the zero-cross time and non-wetting time. The bigger the diameter, the higher the maximum wetting force and the longer the non-wetting time. With the increasing vias’ diameter, the decreasing trend of the zero-cross time can be observed. The obtained results prove that the proposed methodology is appropriate for evaluating the alloys’ solderability in vias, providing a complex view of their wetting behavior during soldering.