An easily testable parallel multiplier

Abstract

The n-by-n parallel multiplier can be usually broken into two blocks, the summand-generator and the summand-counter. The summand-generator generates n/sup 2/ summands and the summand-counter adds them up to produce the final 2n-bit product. The summand-generator is easy to test because all inputs are directly controllable and all faults propagate through summand-counter to primary outputs. However, the summand-counter is difficult to test due to poor controllability. To provide 100% controllability of summands, the summand-generator is modified using one extra input. This new summand-generator can be tested with 19 vectors. With this summand-generator, the summand-counter can be constructed testable using the minimum number of adder cells but no extra device or pin. This summand-counter can be tested with 3n+41 vectors. Thus, a parallel multiplier can be designed testable with 3n+60 vectors using only one extra pin.<>