A Study on an IBIS-like Model to Ensure Signal/Power Integrity for I/O Drivers

Abstract

This paper presents a study on non-linear modeling, reported in the state-of-the-art in the last decade for I/O drivers. The study includes the IBIS-like modeling techniques including package parasitics. The IBIS-like model has been analyzed mathematically and validated using 28 nm CMOS technology of TSMC foundry. For validation purposes, the predriver circuit and the I/O buffers have been simulated with 0.9 V of VDD. The IBIS-like nonlinear models have been created using Simulink® and the results have been compared with the Electronic Design Automation (EDA) tools. The Simulink® results show a Normalized Mean Square Error (NMSE) of - 51.91 dB with 1.63 sec of CPU time for the case of pull-up current, -49.42 dB with 474.34 msec of CPU time for the case of pulldown current response. In the case of output voltage response, the NMSE is - 48.33 dB and 2.12 sec of CPU time.