Low voltage low power neuron circuit design based on subthreshold FGMOS transistors and XOR implementation

Abstract

In this work, design of low-voltage low-power analog artificial neural network (ANN) circuit blocks by using subthreshold floating-gate MOS (FGMOS) transistors and a neuron circuit is implemented. The circuit blocks, four-quadrant analog current multiplier and FGMOS based differential pair, have been designed and simulated in CADENCE environment with TSMC 0.35µm process parameters. Using the proposed neuron circuits a neural network was realized. XOR problem was applied to test accuracy of the network and the results were concluded.