HopliteBuf

Tushar Garg, Saud Wasly, R. Pellizzoni, Nachiket Kapre
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引用次数: 3

Abstract

HopliteBuf is a deflection-free, low-cost, and high-speed FPGA overlay Network-on-chip (NoC) with stall-free buffers. It is an FPGA-friendly 2D unidirectional torus topology built on top of HopliteRT overlay NoC. The stall-free buffers in HopliteBuf are supported by static analysis tools based on network calculus that help determine worst-case FIFO occupancy bounds for a prescribed workload. We implement these FIFOs using cheap LUT SRAMs (Xilinx SRL32s and Intel MLABs) to reduce cost. HopliteBuf is a hybrid microarchitecture that combines the performance benefits of conventional buffered NoCs by using stall-free buffers with the cost advantages of deflection-routed NoCs by retaining the lightweight unidirectional torus topology structure. We present two design variants of the HopliteBuf NoC: (1) single corner-turn FIFO (W → S) and (2) dual corner-turn FIFO (W → S+N). The single corner-turn (W → S) design is simpler and only introduces a buffering requirement for packets changing dimension from the X ring to the downhill Y ring (or West to South). The dual corner-turn variant requires two FIFOs for turning packets going downhill (W → S) as well as uphill (W → N). The dual corner-turn design overcomes the mathematical analysis challenges associated with single corner-turn designs for communication workloads with cyclic dependencies between flow traversal paths at the expense of a small increase in resource cost. Our static analysis delivers bounds that are not only better (in latency) than HopliteRT but also tighter by 2−3×. Across 100 randomly generated flowsets mapped to a 5×5 system size, HopliteBuf is able to route a larger fraction of these flowsets with <128-deep FIFOs, boost worst-case routing latency by ≈ 2× for mutually feasible flowsets, and support a 10% higher injection rate than HopliteRT. At 20% injection rates, HopliteRT is only able to route 1--2% of the flowsets, while HopliteBuf can deliver 40--50% sustainability. When compared to the W → Sbkp backpressure-based router, we observe that our HopliteBuf solution offers 25--30% better feasibility at 30--40% lower LUT cost.
HopliteBuf是一种无偏转、低成本、高速的FPGA覆盖片上网络(NoC),具有无失速缓冲器。它是一种fpga友好的二维单向环面拓扑,建立在HopliteRT覆盖NoC之上。HopliteBuf中的无失速缓冲区由基于网络演算的静态分析工具支持,该工具有助于确定规定工作负载的最坏情况FIFO占用界限。我们使用廉价的LUT ram (Xilinx srl32和Intel MLABs)来实现这些fifo,以降低成本。HopliteBuf是一种混合微架构,它结合了传统缓冲noc的性能优势(通过使用无失速缓冲)和偏转路由noc的成本优势(通过保留轻量级单向环面拓扑结构)。我们提出了HopliteBuf NoC的两种设计变体:(1)单转弯FIFO (W→S)和(2)双转弯FIFO (W→S+N)。单角转弯(W→S)设计更简单,只引入了从X环到下坡Y环(或从西到南)的数据包尺寸变化的缓冲要求。双弯道转弯需要两个fifo来转弯下坡(W→S)和上坡(W→N)的数据包。双弯道转弯设计克服了与单弯道转弯设计相关的数学分析挑战,这些设计适用于具有流遍历路径之间循环依赖关系的通信工作负载,但代价是资源成本的小幅增加。我们的静态分析提供的边界不仅比HopliteRT更好(延迟),而且比HopliteRT严格2 - 3倍。在映射到5×5系统大小的100个随机生成的流集中,HopliteBuf能够通过<128深度的fifo路由更大的流集,将最坏情况路由延迟提高约2倍,并且支持比HopliteRT高10%的注入速率。在20%的注入速率下,HopliteRT只能路由1- 2%的流集,而HopliteBuf可以提供40- 50%的可持续性。与基于W→Sbkp背压的路由器相比,我们观察到我们的HopliteBuf解决方案的可行性提高了25- 30%,LUT成本降低了30- 40%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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