Symbolic fault modeling for switched-capacitor circuits

Abstract

A symbolic construction method allowing for parameter limit operation is proposed. Switched-capacitor circuits can be analyzed with this method by creating a symbolic z-domain transfer function represented in the form of a Binary Decision Diagram (BDD). Manipulating the symbols in BDD can simulate a variety of circuit faults, such as switch faults, capacitor faults, and opamp gain faults. Implementation methods are presented and illustration examples are provided.