A self-reference sensing for improving reliability and bandwidth with 2T2MTJ STT-MRAM cell

Abstract

This paper presents a self-reference read scheme with 2T2MTJ STT-MRAM static gain cell which improves sensing margin and operating speed enough to replace the on-die cache memories and the embedded applications. The proposed self-reference sensing scheme completely suppresses variations and mismatches in MTJs and circuits. The performance is evaluated with the Verilog-A MTJ model and the Monte-Carlo analysis in 65nm CMOS process technology. The proposed circuits show 100mV sensing margin in 5ns tCK, 0.8V VDD and 100% TMR.