Simulation experiments of a high-performance RapidIO-based processing architecture

Abstract

Describes the results of our simulation analysis of a high-performance processing architecture based on the RapidIO network protocol. RapidIO is a 10-Gb/s, low-latency packet-switched interconnect technology designed for processor-to-processor, processor-to-memory, and processor-to-peripheral interconnects. Two network topologies were simulated, a simple network consisting of an 8-port switch and eight processing nodes and a more extensive network consisting of five 8-port switches and 24 processing nodes. The results indicate that latencies as low as 92 ns for a remote 64-bit read request/response transaction may be achieved in an unloaded single-switch system. The effectiveness of various flow control mechanisms provided by the protocol are also explored, and when used in combination, a 10% increase in link utilization is achieved.