Data layout optimization based on the spatio-temporal model of field access

Abstract

Memory access latency is one of the performance bottlenecks of most programs. Improving cache utilization is a common way to improve memory performance. Data layout optimization can improve cache performance based on the locality principle of the memory hierarchy. By analyzing the timestamp information and spatial information of memory access, a field access spatio-temporal model named FASTM was constructed to optimize the data layout of the structure. FASTM consists of three parts: hot data analysis, relative memory access count model and memory access behavior similarity model. A heuristic algorithm based on FASTM is proposed to design the split optimization scheme of the structure. Experimental results on eight benchmarks from SPEC and Olden show that FASTM can reduce cache misses by 57.85% and Translation Lookaside Buffer (TLB) misses by 74.70% on average. The average speedup of program running time is up to 1.37x.