Challenges and key learnings in enabling Low Temperature Solder (LTS) technology at packaging components supply base

Abstract

There has been a great interest in the use of low temperature soldering (LTS) for surface mount technology (SMT) in the past five years. Low temperature solder (LTS) technology improves the package warpage by reducing thermo-mechanical stress during SMT reflow. Several other benefits with LTS include environmental benefits, decreased carbon emissions, and lower electricity consumption. In this study, LTS technology has been evaluated on several electronic components such as, Integrated circuit (IC), memory, ASIC, and passives. Using several LTS formulations, Solder Joint Reliability (SJR) properties were characterized EOL as well as after reliability testing at components suppliers. Several different package types (i.e. QFN, LGA, CSP, WLCSP etc.), and surface finishes were used in this study. For some of the IC components, different types of packages were evaluated: land grid array (LGA) and quad flat no leads (QFN). Different paste formulations having (35–58 wt.% Bi content) were used in these evaluations and SAC305 was the POR/control leg used. Temperature cycle and other reliability data showed promising results with comparable data for both LTS and SAC legs. The goal in this paper is to document some of the challenges in components supply chain enabling and key learnings on the factors that modulate LTS solder joint reliability for various components during SMT process.