{"title":"High/low-side hybrid output transistor with high thermal-SOA","authors":"S. Wada, Katsumi Ikegaya, T. Oshima, Y. Kobayashi","doi":"10.23919/ISPSD.2017.7988897","DOIUrl":null,"url":null,"abstract":"A novel high/low-side hybrid output transistor with high thermal safe operating area (SOA) performance was developed. The output transistor was designed by alternatively arranging high- and low-side transistors to enhance the thermal diffusion from self-heated transistors. A 42% increase in the failure energy of the conventional transistor was obtained at 300-μs short-circuit duration, and a further 10–15% improvement was obtained by introducing a Cu redistribution layer (Cu-RDL) of power metal. A 3D-thermal simulation demonstrated that the peak junction temperature was reduced by around 100°C in the hybrid output transistor during clamp inductive switching. The energy capability of the hybrid output transistor also improved from 18 to 31 mJ in the solenoid driver circuit.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ISPSD.2017.7988897","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A novel high/low-side hybrid output transistor with high thermal safe operating area (SOA) performance was developed. The output transistor was designed by alternatively arranging high- and low-side transistors to enhance the thermal diffusion from self-heated transistors. A 42% increase in the failure energy of the conventional transistor was obtained at 300-μs short-circuit duration, and a further 10–15% improvement was obtained by introducing a Cu redistribution layer (Cu-RDL) of power metal. A 3D-thermal simulation demonstrated that the peak junction temperature was reduced by around 100°C in the hybrid output transistor during clamp inductive switching. The energy capability of the hybrid output transistor also improved from 18 to 31 mJ in the solenoid driver circuit.