Adapting the Hyper-Ring Interconnect for Many-Core Processors

Abstract

This paper makes the case for the Hyper-Ring as the interconnect or NoC for many-cores. While other prominent candidates for many-core interconnect such as the torus and mesh have superior bisection bandwidth to the HR, their cost, number of links and chip area are much higher than the HR. The worst-case latency or maximum hop count is relatively inferior on the mesh, while that of the HR is comparative to that of the torus for about a 100 core nodes. Moreover, the HR resembles more the LANs and WANs which have dedicated gateway or router nodes. We present a many-core floorplan where adjacent pairs of cores share an L2 cache memory and where the cores are interconnected according the HR topology. We also address L2 cache partitioning and coherence in HR-connected many-core processors and how such a processor can be tolerant of faulty links and nodes. The HR-connected many-core processor is naturally tolerant of core and link faults owing to its double second directional rings. To keep the same amount of operational hardware and the same performance levels in the presence of faults, we present a circuit for bypassing faulty cores and replacing them by spare cores.