A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity

Abstract

A flip-flop using a combination of thin and thick gate transistors combines high performance and low standby power. Setup and hold times are controlled by the master latch implemented in high performance transistors, while a thick gate slave latch provides state retention at low standby power when the high performance circuit power supply is gated off. The design has reduced circuit and power-down control complexity compared to previously described circuits using thick gate shadow latches for low standby power state storage. Measured test chip results on a foundry 130 nm process prove the viability of the design. The thick gate shadow latches are shown to have good retention capability at low supply voltages, suggesting that reduced shadow latch supply voltage during standby will be effective at mitigating the drain to bulk leakage components that are increasingly limiting for low power standby modes.