A low-power interface circuit for piezoresistive transducers

Abstract

This paper presents the design and development of a low-power interface circuit for piezoresistive transducers. This circuit combines the chopping technique with the correlated double sampling (CDS) technique in order to eliminate both the amplifier offset and the chopper ripple at the sampling frequency. In addition, programmable current sources compensate for the transducer offset and the low frequency components coming from environmental conditions thus allowing the readout of very weak input signals with high resolution (0.45μV) at a total power consumption of 200 μW.