Linear time fault simulation algorithm using a content addressable memory

N. Ishiura, S. Yajima
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引用次数: 3

Abstract

The authors present a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The new algorithm attempts to reduce the computation time by processing many faults at a time on the assumption that a content addressable memory can be regarded as a single instruction multiple data (SIMD) type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is comparable to that of a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.<>
使用内容可寻址存储器的线性时间故障仿真算法
针对门级同步时序电路的零延迟故障仿真问题,提出了一种基于内容可寻址存储器的快速故障仿真算法。该算法将内容可寻址存储器视为单指令多数据(SIMD)型并行计算机,试图通过一次处理多个故障来减少计算时间。根据理论估计,基于该算法的仿真器的速度性能与在矢量超级计算机上实现的快速故障模拟器在2400门电路中的速度性能相当。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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