{"title":"VDDQ: a built-in self-test scheme for analog on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard","authors":"G. Acevedo, J. Ramírez-Angulo","doi":"10.1109/ICCDCS.2002.1004083","DOIUrl":null,"url":null,"abstract":"An innovative self-diagnostic method called VDDQ is presented. The proposed method is compliant with the IEEE 1149.4 mixed-signal test bus standard. It performs a pass or fail function of the analog circuit. The VDDQ method sequentially senses the quiescent voltage of several nodes on the circuit under test (CUT) and compares them with their nominal value. The method produces a 10 bit digital vector, with nodal information including a pass or fail flag, plus the analog voltage sensed. Simulation results are provided for the flag and amplifier circuit used for the design of the testing circuit. Through simulations, this testing scheme has performed a test per node every millisecond. This will potentially allow a defect free IC to enter the market in significantly less time than with conventional testing methods.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCDCS.2002.1004083","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
An innovative self-diagnostic method called VDDQ is presented. The proposed method is compliant with the IEEE 1149.4 mixed-signal test bus standard. It performs a pass or fail function of the analog circuit. The VDDQ method sequentially senses the quiescent voltage of several nodes on the circuit under test (CUT) and compares them with their nominal value. The method produces a 10 bit digital vector, with nodal information including a pass or fail flag, plus the analog voltage sensed. Simulation results are provided for the flag and amplifier circuit used for the design of the testing circuit. Through simulations, this testing scheme has performed a test per node every millisecond. This will potentially allow a defect free IC to enter the market in significantly less time than with conventional testing methods.