Functional-based ATPG for path delay faults

Abstract

A novel methodology for non-enumerative ATPG for path delay faults is presented. Tests are generated by manipulating, in a systematic yet simple way, sets of pairs of functions. Each pair of functions represents the constraints to be satisfied by the non-enumerative delay fault test for each time frame of a transition. A test that detects many faults is generated from each pair of functions. A current ROBDD-based implementation of this technique is used to analyze the delay fault testability of the ISCAS'85 benchmark circuits.