{"title":"Low Power Reconfigurable Multiplier for Network on Chip Architecture","authors":"R. Sangeetha, T. Thangam","doi":"10.26821/IJSHRE.7.5.2019.7502","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":442258,"journal":{"name":"International Journal of Software & Hardware Research in Engineering","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Software & Hardware Research in Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.26821/IJSHRE.7.5.2019.7502","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}