{"title":"A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias","authors":"Kentaro Nagai, Jun Shiomi, H. Onodera","doi":"10.1109/APCCAS50809.2020.9301711","DOIUrl":null,"url":null,"abstract":"This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently so that the BBG can minimize total energy consumption under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which results in low energy consumption and small area. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor implemented on the same chip show that the proposed BBG can reduce energy consumption close to a minimum where the amount of excess energy is 3%. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS50809.2020.9301711","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently so that the BBG can minimize total energy consumption under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which results in low energy consumption and small area. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor implemented on the same chip show that the proposed BBG can reduce energy consumption close to a minimum where the amount of excess energy is 3%. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.