A reconfiguration solution for CMOS frequency synthesizers in cognitive radios

Abstract

This article proposes a reconfiguration solution for CMOS frequency synthesizer with a hybrid architecture which is a combination of a Direct Digital Synthesizer (DDS) and a Phase Locked Loop (PLL). The DDS is implemented in FPGA platform functioning a reference frequency to the PLL. The PLL is designed using CMOS technology, being reconfigurable to accelerate tuning speed. Instead of employing a hardware-based lock detector, a software algorithm is used to determine the switching time and to optimize the frequency tuning speed, consuming energy or limited pick power. This PLL is used in cognitive radio for spectrum sensing function.