A Structure Design of Safety PLC with Heterogeneous Redundant Dual-Processor

Abstract

Structure of safety PLC with heterogeneous redundant dual-processor is proposed based on the shortcomings of conventional PLC in practical application and the requirement of PLC for safety and reliability control. In the traditional PLC system using ARM processor, a 32-bit RISC processor based on FPGA is added, which to form a redundancy structure of heterogeneous dual-processor. This structure makes PLC redundant processing of logic, and satisfies the safety requirements of equipment and personnel for PLC control applications. The experiments show that the system's task scheduling cycle is in the range of 7.922ms to 8.053ms, the jitter error is in the range of −0.078ms to 0.053ms, and the execution cycle of real-time periodic logic is in the range of 1.258ms to 2.005ms, which can meet the requirements of safety and reliability control.