{"title":"DAC Circuit with Multi-threshold Voltage for TFT-LCD Driver IC","authors":"Wei Wu, T. Wei, Xiaoya Fan, Fulong Chen","doi":"10.1109/CADCG.2007.4407899","DOIUrl":null,"url":null,"abstract":"A new DAC circuit with multi-threshold voltage for large panel TFT-CLD source driver is proposed based on its binary-tree structural characters. Through setting different bulk voltages VB for different CMOS analog switches, the threshold voltages and the on-resistance of CMOS analog switches are reduced and the signal transmission speed from resistance network to output buffer is increased greatly. Physical implementation of this structure is simple and no extra components are required. The proposed DAC circuit structure with 10-bit resolution is designed and simulated using 0.35 mum 13.5 V CMOS high-voltage process, the SPICE simulation results show that the step response delay time is reduced from 35 ns to 17.4 ns (by 50%), as compared to conventional DAC structure.","PeriodicalId":143046,"journal":{"name":"2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CADCG.2007.4407899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A new DAC circuit with multi-threshold voltage for large panel TFT-CLD source driver is proposed based on its binary-tree structural characters. Through setting different bulk voltages VB for different CMOS analog switches, the threshold voltages and the on-resistance of CMOS analog switches are reduced and the signal transmission speed from resistance network to output buffer is increased greatly. Physical implementation of this structure is simple and no extra components are required. The proposed DAC circuit structure with 10-bit resolution is designed and simulated using 0.35 mum 13.5 V CMOS high-voltage process, the SPICE simulation results show that the step response delay time is reduced from 35 ns to 17.4 ns (by 50%), as compared to conventional DAC structure.
基于二叉树结构特点,提出了一种适用于大面板tft - lcd源驱动器的多阈值电压DAC电路。通过对不同的CMOS模拟开关设置不同的本体电压VB,降低了CMOS模拟开关的阈值电压和导通电阻,大大提高了信号从电阻网络到输出缓冲器的传输速度。这种结构的物理实现很简单,不需要额外的组件。采用0.35 μ m 13.5 V CMOS高压工艺设计并仿真了10位分辨率的DAC电路结构,SPICE仿真结果表明,与传统的DAC结构相比,该电路的阶跃响应延迟时间从35 ns减少到17.4 ns(减少了50%)。