Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA

Abstract

We empirically evaluated the energy- and area-saving effect of Dynamic Partial Reconfiguration (DPR) of a 28-nm process FPGA. DPR is a technology where a portion of the entire circuit is replaced with another one, while the other parts of the circuit still continue running. Using DPR, different functionalities are not necessarily implemented at once; only required modules need be implemented on the FPGA. Therefore, a DPR system requires less hardware resources, and consequently, can save the power consumption of the system. We explored the effectiveness of DPR in saving energy and area of a multi-algorithm cryptoprocessor on Kintex-7 FPGA on SASEBO-GIII board. The cryptoprocessor supports the six ISO/IEC 18033-3 block cipher algorithms: AES, Camellia, SEED, TDEA, MISTY1, and CAST-128. In a DPR cryptoprocessor, only one cipher module is implemented at once, and it is overwritten when a different algorithm is required. Compared to the non-DPR cryptoprocessor, the DPR cryptoprocessor can reduce up to 74% hardware resource (slice) and 3.4% energy consumption.