Simplified path metric updating in the M algorithm for VLSI implementation

Abstract

A VLSI structure for path metric updating in the M algorithm is presented. The architecture is based on the combination of a modified Batcher's (1968) odd-even merging network and a bitonic selection procedure. A feature of the trellis structure allows to replace an existing solution based on two 2M-item sorting operations by three M-item sorting operations with an additional one-layer bitonic merge. These three sorting networks and the bitonic merging procedure permit a reduction of up to 50% in hardware complexity.