FPGA implementation of K-Winners-Take-All neural network based on linear programming formulation

Abstract

K-Winner-take-all (kWTA) is an operation that identifies the k largest inputs from multiple input signals. It has important applications in machine learning, statistics filtering and sorting, etc. As the number of inputs becomes large and the selection process should be operated in real time, parallel algorithms are desirable. For these reasons, many neural network algorithms have been proposed to solve kWTA. Compared with software simulations, the hardware implementation is capable of a high degree of parallelism. There are many hardware implementations that have been proposed, such as digital chips, analog chips, hybrids chips, FPGA based chips, and (non-electronic) optical chips implementation. Compared with other hardware implementations, the FPGA provides an effective programmable resource, together with a fast prototyping and rapid system deployment. In this paper, a new hardware implementation technique for a typical neural network of kWTA using a field-programmable-gate-array (FPGA) chip is proposed. Experimental results show that the proposed hardware implementation method has a high degree of parallelism and fast performance.