FPGA Implementation of Area and Speed Efficient CORDIC Algorithm

Abstract

This paper proposes an efficient serial and parallel Coordinate Rotation Digital Computer (CORDIC) architecture that is both area utilization and delay efficient and compares the two architectures. CORDIC algorithm is an integral part of DSP (digital signal processing) applications since it helps to perform complex operations such as trigonometric, logarithmic, exponential, and many other mathematical functions with a multiplier less architecture and using simple hardware blocks. In this project 32-bit floating-point serial and parallel CORDIC architecture is implemented on Field programmable gate array device (FPGA) with the help of different adders such as Carry Save adder (CSA), Carry Select adder (CSLA), Han Carlson adder, Sklansky and Ladner Fischer adder in place of the conventional ripple carry adder block used in CORDIC architecture to come up with an area and speed efficient CORDIC architecture. The proposed architecture with Ladner Fischer adder gives 4.7 percent area utilization improvement compared to other parallel prefix adders in serial CORDIC architecture and parallel CORDIC architecture. It also gives 43.5 percent lesser delay compared to serial CORDIC architecture implemented with Carry save adder and 43.9 percent lesser delay than parallel CORDIC architecture implemented with carry-save adder.