A novel digital controlled technique for operational amplifier compensation

Abstract

In this paper, a method for operational amplifier compensation is described. An operational amplifier having an offset as high as /spl plusmn/20 mV can be compensated to have a residual offset of as low as /spl plusmn/1 mV. The offset is achieved by trimming the currents in the active loads of the differential pair stage of the op-amp. The trimming currents are obtained by means of a series of binary weighted current sinks. The result of compensation can be observed digitally. and the trim data that is needed to switch on or off the current sinks can also be sent serially in digital format. In this paper, a chip has been designed which incorporates the afore-mentioned compensation technique, and the initial version of the chip without the digital interface logic has been fabricated using AMI 0.5 /spl mu/m CMOS technology.