A 5.2GHz CMOS fractional-n frequency synthesizer with a MASH delta-sigma modulator

Abstract

A 5-GHz CMOS fractional-N frequency synthesizer with a delta-sigma modulator is designed in this paper. The frequency dividers are composed of an injection-locked frequency divider and a programmable divider. In consideration of low power consumption, we use an injection-locked frequency divider as the first stage prescaler. The loop filter is a second-order passive filter. The delta-sigma modulator is MASH 1-1-1 architecture. The VCO exhibits a phase noise of-116dBc/Hz at 1MHz offset frequency and an output frequency ranges from 4.91GHz to 5.38GHz. TSMC 0.18-mum CMOS process is used for this frequency synthesizer design and simulation. The frequency resolution of this fractional-N frequency synthesizer is 27 KHz and the locking time is 8 mus.