Yield-reliability modeling for fault tolerant integrated circuits

T. S. Barnett, A. Singh, V. Nelson
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引用次数: 6

Abstract

An integrated yield-reliability model for defect tolerant integrated circuits is presented that allows one to estimate the yield following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures and defects causing infant mortality failures. The two-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter /spl alpha/, while known to play a key role in accurately determining wafer probe yields of defect tolerant chips, is shown for the first time. to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ significantly from calculations that ignore clustering.
容错集成电路的屈服可靠性建模
提出了一种容限缺陷集成电路的成品率-可靠性综合模型,该模型可以估计晶圆探头和烧蚀测试后的成品率。该模型基于长期观察到的缺陷聚类和实验验证的导致晶圆探针失效的缺陷与导致婴儿死亡失效的缺陷之间的关系。用双参数负二项分布来描述半导体晶圆上缺陷的分布。聚类参数/spl alpha/,虽然已知在准确确定缺陷容限芯片的晶圆探头良率方面起关键作用,但首次显示。在决定倦怠效应方面扮演类似的角色。数值结果表明,聚类模型预测的婴儿死亡率失败数与忽略聚类的计算结果有显著差异。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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