Lahiru Nawarathna, Nalith Udugampola, Yasara Yasawardhana, Thilina W. Weerasinghe, S. Thayaparan
{"title":"Low-Cost Automatic Test Equipment for Digital ICs Using DE0-Nano - Altera Cyclone IV FPGA","authors":"Lahiru Nawarathna, Nalith Udugampola, Yasara Yasawardhana, Thilina W. Weerasinghe, S. Thayaparan","doi":"10.1109/ICECIE52348.2021.9664695","DOIUrl":null,"url":null,"abstract":"With the advancement of technology, the digital Integrated Circuit (IC) design process has become more complex and denser. Hence, the IC testing procedure requires high-end test equipment to validate the accuracy and reliability of the manufactured components. Testers with such capabilities usually cost millions of dollars. In this paper, the authors have presented a low-cost hardware and software solution for digital IC testing. Digital ICs which operate under the 100MHz range can be easily tested in the digital domain with the FPGA-based test environment. The presented design comprises of a scalable architecture with a set of clock synchronized Altera DE0-Nano Field Programmable Gate Arrays (FPGAs) which handles the digital testing of Device Under Test (DUT) at a low cost. The digital test patterns are generated inside a computer, which transfers them to the FPGA environment and feeds them to DUT. The resulting patterns captured by the FPGAs are sent back to the computer, where they are compared with the expected results. The design prototype made by the authors of this paper consists of 48 digital input/ output channels which can source and capture bit streams parallelly to test digital ICs up to 100MHz frequency. Furthermore, the prototyped tester consists of electrical measuring instruments that can measure voltages with a 10mV accuracy and currents with a 10µA accuracy.","PeriodicalId":309754,"journal":{"name":"2021 3rd International Conference on Electrical, Control and Instrumentation Engineering (ICECIE)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 3rd International Conference on Electrical, Control and Instrumentation Engineering (ICECIE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECIE52348.2021.9664695","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
With the advancement of technology, the digital Integrated Circuit (IC) design process has become more complex and denser. Hence, the IC testing procedure requires high-end test equipment to validate the accuracy and reliability of the manufactured components. Testers with such capabilities usually cost millions of dollars. In this paper, the authors have presented a low-cost hardware and software solution for digital IC testing. Digital ICs which operate under the 100MHz range can be easily tested in the digital domain with the FPGA-based test environment. The presented design comprises of a scalable architecture with a set of clock synchronized Altera DE0-Nano Field Programmable Gate Arrays (FPGAs) which handles the digital testing of Device Under Test (DUT) at a low cost. The digital test patterns are generated inside a computer, which transfers them to the FPGA environment and feeds them to DUT. The resulting patterns captured by the FPGAs are sent back to the computer, where they are compared with the expected results. The design prototype made by the authors of this paper consists of 48 digital input/ output channels which can source and capture bit streams parallelly to test digital ICs up to 100MHz frequency. Furthermore, the prototyped tester consists of electrical measuring instruments that can measure voltages with a 10mV accuracy and currents with a 10µA accuracy.