Flexible design of SPARC cores: a quantitative study

Abstract

In this paper we present experimental results obtained during the modelling, design and implementation of a full set of versions of SPARC v8 integer unit core aimed for embedded applications in digital media products. VHDL has been the description language, Synopsis tools those for the logical synthesis, and Duet Technologies' Epoch has been used for the physical layout of the final circuits. They have been mapped to a 0.35 /spl mu/m, three metal layers process. The quantitative results given characterize suitable points in the design space. They show how much microarchitecture, design, datapath granularity and module decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modelling techniques based on configurable VHDL descriptions.