Area optimization of comparator layout design by using Cadence Virtuoso tools in 45 nanometer process technology

Abstract

This paper presents the area optimization of comparator layout design. Nowadays, technology is continuously developing to improve the quality of human’s life. Electronic devices tend to design in smaller size, lower cost and higher performance. Therefore, layout design plays an important role to design the electronic devices in smaller size, lower cost, and higher performance. This is because when the layout size decreases, the number of chips can be produced by one semiconductor wafer increases and the cost of integrated circuits chip decreases. This project implements the techniques to optimize the area comparator layout which are diffusion sharing, legging and flip the sub-cells by using Cadence Virtuoso tools in 45 nanometer process technology. Based on the result, the total area optimization of comparator layout by comparison the area that given when generated layout from schematic with the area of finalize layout is 67.10%.