Design of configurable, network based interconnection modules for communication centric System-on-Chip applications

Abstract

In recent years, System-on-Chip design architectures have increasingly become communication centric. To support such designs, a configurable and scalable interconnect backbone is required. Intellectual Property cores for on chip communication, provided by major field programmable gate array vendors are limited to shared bus or point to point interconnect protocols. To provide network oriented interconnect fabric, we propose a configurable and scalable, network based interconnect module. The interconnections can be configured to four popular on-chip network topologies: mesh, torus, ring and fat-tree. A parameterized and customizable wormhole router is designed, with variable number of ports and link width to support the four networks. A hardware simulator has been designed for in-situ testing of the interconnect module. Two state of art implementation platforms viz Virtex-6 Field programmable gate array and a full custom implementation using 32nm CMOS process has been used to characterize the module. We report area and power dissipation of the module configured to the four topologies, in the two platforms.