A dynamically configurable-radix pipelined FFT algorithm for real time applications

Abstract

An efficient pipelined Fast Fourier Transform with a dynamically configurable-radix processing element is presented. The architectural design used is the single-path delay feedback. The proposed design significantly optimizes the latency and the hardware utilization of multipliers to 87.5% with a simple and low cost architecture. The proposed architecture is scalable to support multiples of 1024 points using additional stages. The proposed design was implemented on an FPGA. Furthermore, additional stages could be added to reach any FFT size.