NoC-based many-core processor using CUSPARC architecture

Abstract

This paper introduces CUSPARC-M, a many-core message-passing processor based on the Cairo University SPARC processor, CUSPARC, core. CUSPARC-M consists of 16 cores arranged in 4×4 mesh architecture. A Network-on-Chip (NoC) that incorporates X-Y routing, wormhole switching and dynamic virtual channels for flow control provides intra-chip communication. The design is synthesized using TSMC 65nm LP kit achieving power consumption of 13.68× and area of 17× compared to CUSPARC. The NoC consumes only 5.2% of the total power. Simulating a 16-block JPEG encoder on 12 cores of CUSPARCM yielded up to 8.72× speedup factor relative to the single-core version.