IEEE-754 Half-Precision Floating-Point Low-Latency Reciprocal Square Root IP-Core

Abstract

In different matrix-decomposition techniques for wireless-communication systems, the reciprocal square root (RSR) is a fundamental and recurrent operation, as well in gaming and signal processing systems computation of the RSR is required. Most reported RSR architectures are focused on accelerating high-precision floating-point (FP) units. The IEEE 754–2008 half-precision FP standard offers larger dynamic range than fixed-point systems, fewer hardware resources than single-precision FP and enough precision for some applications. This article reports the FPGA implementation of a low-latency, half-precision floating-point RSR unit. The implementation results show that the proposed design exhibits lower latency and better throughput than Intel and Xilinx RSR IP cores.