Clamping Modulation Scheme for Low Speed Operation of Dual Inverter fed Drives

Abstract

Conventional pulse width modulation (PWM) schemes for dual inverter fed drive synthesise the reference voltage as a switched average of minimum three voltage vectors from individual inverters. As a result, the number of transitions in the inverter increases. This paper introduces a family of PWM methods, where the reference voltage is synthesised as a switched average of only two voltage vectors from individual inverter. This leads to simultaneous clamping of two phases, thus reducing the number of switching transitions in the inverter. The concept and realisation of the proposed PWM are discussed and compared with conventional bus clamping PWM methods on the basis of inverter power loss and common mode voltage generation. The proposed PWM is experimentally validated on an open end winding induction motor drive operating with open loop control. Synchronised carrier modulation is considered for PWM generation.