An efficient FPGA based NoC architecture for data communication

Abstract

In today's real time world network on chip (NoC) plays a major role in fast communication between entities. The need for NoC hardware is in demand based on requirement for fast communication with large data bandwidth. In this paper, an efficient field programmable gate array (FPGA) based NoC architecture for data communication is proposed. The router is designed with 4 ports using proposed controller unit, novel first-in first-out (FIFO) architecture and XY routing logic. The proposed controller unit comprises of MUX based architecture to support the data transfer in East, West, North and South directions using respective select lines with flip-flops connected to the output of multiplexers to achieve delay synchronization. A novel FIFO architecture is designed using a counter and decision unit which are used to keep track of incoming data using signal mem_empty or mem_full. The XY routing logic is used to communicate between the routers and a test sample data is chosen to validate the routing path between source and destination using XY routing logic. The proposed routing architecture is tested on SPARTAN-6-XC6SLX45 board. It is observed that the performance parameters such as slice registers, power dissipation and maximum operating frequency are 290, 38.35 mW and 220.729 MHz respectively.