A statistical MOS model for CAD of submicrometer analog IC's

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI:10.1109/MWSCAS.2001.986333

P. Crippa, C. Turchetti, M. Conti

引用次数: 2

Abstract

A novel statistical model for MOS transistor drain current has been developed that allows us to explore IC architectures and study the effects of technological variations on the system performance without using time-consuming Monte Carlo simulations. Characterizing this model only requires a cheap and simple estimation of the mean value and autocorrelation function of a single stochastic process describing all the process/device variations.

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用于亚微米模拟集成电路CAD的统计MOS模型

开发了一种新的MOS晶体管漏极电流统计模型，使我们能够探索IC架构并研究技术变化对系统性能的影响，而无需使用耗时的蒙特卡罗模拟。表征该模型只需要对描述所有过程/设备变化的单个随机过程的平均值和自相关函数进行廉价和简单的估计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

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