Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation

C. Ho, Venkatraman Govindaraju, Tony Nowatzki, R. Nagaraju, Zachary Marzec, Preeti Agarwal, Chris Frericks, Ryan Cofell, K. Sankaralingam
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引用次数: 24

Abstract

Specialization and accelerators are being proposed as an effective way to address the slowdown of Dennard scaling. DySER is one such accelerator, which dynamically synthesizes large compound functional units to match program regions, using a co-designed compiler and microarchitecture. We have completed a full prototype implementation of DySER integrated into the OpenSPARC processor (called SPARC-DySER), a co-designed compiler in LLVM, and a detailed performance evaluation on an FPGA system, which runs an Ubuntu Linux distribution and full applications. Through the prototype, this paper evaluates the fundamental principles of DySER acceleration. Our two key findings are: i) the DySER execution model and microarchitecture provides energy efficient speedups and the integration of DySER does not introduce overheads - overall, DySER's performance improvement to OpenSPARC is 6X, consuming only 200mW ; ii) on the compiler side, the DySER compiler is effective at extracting computationally intensive regular and irregular code. For non-computationally intense irregular code, two control flow shapes curtail the compiler's effectiveness, and we identify potential adaptive mechanisms. Finally, our experience of bringing up an end-to-end prototype of an ISA-exposed accelerator has made clear that two particular artifacts are greatly needed to perform this type of design more quickly and effectively: 1) Open-source implementations of high-performance baseline processors, and 2) Declarative tools for quickly specifying combinations of known compiler transforms.
一个d斯勒FPGA原型系统的性能评估,包括编译器、微架构和硬件实现
专业化和加速器被提议作为解决登纳德尺度放缓的有效方法。DySER就是这样一个加速器,它使用协同设计的编译器和微体系结构,动态地合成大型复合功能单元来匹配程序区域。我们已经完成了一个集成到OpenSPARC处理器(称为SPARC-DySER)的完整原型实现,一个在LLVM中共同设计的编译器,并在一个运行Ubuntu Linux发行版和完整应用程序的FPGA系统上进行了详细的性能评估。通过样机,对daser加速的基本原理进行了评价。我们的两个主要发现是:i) DySER执行模型和微架构提供了节能加速,并且DySER的集成不会引入开销-总体而言,DySER对OpenSPARC的性能改进是6倍,仅消耗200mW;ii)在编译器方面,daser编译器可以有效地提取计算密集型的规则和不规则代码。对于非计算密集型的不规则代码,两种控制流形状限制了编译器的有效性,并确定了潜在的自适应机制。最后,我们提出一个isa公开的加速器的端到端原型的经验清楚地表明,为了更快更有效地执行这种类型的设计,非常需要两个特定的工件:1)高性能基线处理器的开源实现,以及2)用于快速指定已知编译器转换组合的声明性工具。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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